HYB39S64160AT-10 SIEMENS [Siemens Semiconductor Group], HYB39S64160AT-10 Datasheet - Page 26

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HYB39S64160AT-10

Manufacturer Part Number
HYB39S64160AT-10
Description
64 MBit Synchronous DRAM
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
CLK
COMMAND
6.2 Write Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3
7.1 Burst Write with Auto-Precharge
Burst Length = 2, CAS latency = 2, 3)
CLK
COMMAND
Semiconductor Group
CAS latency = 3
t
DQ’s
CAS latency = 2
t
CK3,
CK2,
DQ’s
DQ’s
BANK A
ACTIVE
T0
T0
NOP
T1
WRITE A
T1
Input data for the Write is ignored.
NOP
DIN A 0
DIN A 0
T2
T2
READ B
NOP
don’t care
don’t care
Auto-Precharge
T3
WRITE A
DIN A 0
T3
NOP
don’t care
26
T4
DIN A 1
NOP
T4
NOP
DOUT B 0
t
WR
Input data must be removed from the DQ’s at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
T5
NOP
T5
NOP
DOUT B 1
DOUT B 0
64MBit Synchronous DRAM
HYB39S64400/800/160AT(L)
T6
*
NOP
Begin Autoprecharge
Bank can be reactivated after trp
T6
DOUT B 2
DOUT B 1
NOP
t
RP
T7
NOP
T7
DOUT B 3
DOUT B 2
NOP
T8
NOP
T8
DOUT B 3
NOP

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