HYB39S64160AT-10 SIEMENS [Siemens Semiconductor Group], HYB39S64160AT-10 Datasheet - Page 8

• Manufacturer Part Number: HYB39S64160AT-10
• Description: 64 MBit Synchronous DRAM
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Row Activate (ACT)
Read (READ)
Read w/ Autoprecharge
(READA)
Write (WRITE)
Write w/ Autoprecharge
(WRITEA)
Row Precharge (PRE)
Precharge All (PREA)
Mode Register Set (MRS)
No Operation (NOP)
Device Deselect (INHBT)
Auto Refresh (REFA)
Self Refresh Entry (REFS-EN)
Self Refresh Exit (REFS-EX)
Power Down Entry (PDN-EN)
Power Down Exit (PDN-EX)
Data Write/Output Enable
Data Write/Output Disable
Note:
1. V = Valid, x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before
3. This is the state of the banks designated by BS0, BS1 signals.
4. Device state is Full Page Burst operation
5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode cycle
Semiconductor Group
Operation
device is clock suspend mode.
the commands are provided.
Active
Active
Active
Active
Active
(Power
Device
Down)
Active
Active
Refr.)
State
Idle
(Self
Any
Any
Any
Any
Any
Idle
Idle
Idle
Idle
Idle
3
3
3
3
3
5
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
CKE
X
X
X
X
X
X
X
X
X
X
H
H
H
X
X
n
L
L
8
CS
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
H
H
H
H
H
X
H
X
H
X
H
X
L
L
L
L
X
L
L
X
64MBit Synchronous DRAM
HYB39S64400/800/160AT(L)
CAS
H
H
H
H
H
H
H
X
X
X
X
X
X
L
L
L
L
L
L
L
WE
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
L
L
L
DQM A0-9,
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
A11
V
V
V
V
V
X
X
V
X
X
X
X
X
X
X
X
X
A10
V
H
H
H
V
X
X
X
X
X
X
X
X
X
L
L
L
BS0
BS1
V
V
V
V
V
V
X
V
X
X
X
X
X
X
X
X
X