HYB39S64160AT-10 SIEMENS [Siemens Semiconductor Group], HYB39S64160AT-10 Datasheet - Page 7

• Manufacturer Part Number: HYB39S64160AT-10
• Description: 64 MBit Synchronous DRAM
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Signal Pin Description
Semiconductor Group
VDD,VSS Supply
CAS, WE
A0 - A11
BA0,BA1
UDQM
LDQM
VDDQ
VSSQ
DQM
CKE
RAS,
DQx
CLK
Pin
CS
Supply
Output
Type Signal Polarity
Input
Input
Input
Input
Input
Input
Input
Input
Pulse
Pulse
Pulse
Pulse
Level
Level
Level
Level
—
Positive
Active
Active
Active
Active
Edge
High
High
Low
Low
—
—
—
—
The system clock input. All of the SDRAM inputs are sampled on the
rising edge of the clock.
Activates the CLK signal when high and deactivates the CLK signal
when low, thereby initiates either the Power Down mode, Suspend
mode, or the Self Refresh mode.
CS enables the command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new
commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS, RAS, and
WE define the command to be executed by the SDRAM.
During a Bank Activate command cycle, A0-A11 defines the row
address (RA0-RA11) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column
address (CA0-CAn) when sampled at the rising clock edge.CAn
depends from the SDRAM organisation:
In addition to the column address, A10(=AP) is used to invoke
autoprecharge operation at the end of the burst read or write cycle. If
A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to
be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 (=AP) is used in conjunction
with BA0 and BA1 to control which bank(s) to precharge. If A10 is high,
all four banks will be precharged regardless of the state of BA0 and BA1.
If A10 is low, then BA0 and BA1 are used to define which bank to
precharge.
Bank Select (BS) Inputs. Selects which bank is to be active.
Data Input/Output pins operate in the same manner as on conventional
DRAMs.
The Data Input/Output mask places the DQ buffers in a high impedance
state when sampled high. In Read mode, DQM has a latency of two
clock cycles and controls the output buffers like an output enable. In
Write mode, DQM has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the write operation
if DQM is high.
One DQM input it present in x4 and x8 SDRAMs, LDQM and UDQM
controls the lower and upper bytes in x16 SDRAMs.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
16M x 4 SDRAM
8M x 8 SDRAM
4M x 16 SDRAM CAn = CA7
7
CAn = CA9
CAn = CA8
64MBit Synchronous DRAM
HYB39S64400/800/160AT(L)
Function
(Page Length = 1024 bits)
(Page Length = 512 bits)
(Page Length = 256 bits)