R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 12

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.4
6.5
6.6
6.7
6.8
6.9
6.10 Usage Note......................................................................................................................... 160
Section 7 User Break Controller (UBC)............................................................ 161
7.1
7.2
7.3
Rev. 2.00 Sep. 07, 2007 Page xii of xxviii
6.3.7
6.3.8
6.3.9
6.3.10 DMA Transfer Request Enable Register 0 (DREQER0) ...................................... 129
6.3.11 DMA Transfer Request Enable Register 1 (DREQER1) ...................................... 130
6.3.12 DMA Transfer Request Enable Register 2 (DREQER2) ...................................... 131
6.3.13 DMA Transfer Request Enable Register 3 (DREQER3) ...................................... 132
Interrupt Sources................................................................................................................ 133
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
Interrupt Exception Handling Vector Table and Priority................................................... 136
Operation ........................................................................................................................... 146
6.6.1
6.6.2
Interrupt Response Time.................................................................................................... 149
Register Banks ................................................................................................................... 154
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
Data Transfer with Interrupt Request Signals.................................................................... 159
6.9.1
6.9.2
6.10.1 Timing to Clear an Interrupt Source ..................................................................... 160
Features.............................................................................................................................. 161
Input/Output Pin ................................................................................................................ 163
Register Descriptions......................................................................................................... 163
7.3.1
7.3.2
7.3.3
PINT Interrupt Request Register (PIRR) .............................................................. 126
Bank Control Register (IBCR).............................................................................. 127
Bank Number Register (IBNR) ............................................................................ 128
NMI Interrupt........................................................................................................ 133
User Break Interrupt ............................................................................................. 133
H-UDI Interrupt .................................................................................................... 133
IRQ Interrupts....................................................................................................... 134
PINT Interrupts..................................................................................................... 135
On-Chip Peripheral Module Interrupts ................................................................. 135
Interrupt Operation Sequence ............................................................................... 146
Stack after Interrupt Exception Handling ............................................................. 148
Register Banks and Bank Control Registers ......................................................... 155
Bank Save and Restore Operations....................................................................... 155
Save and Restore Operations after Saving to All Banks....................................... 157
Register Bank Exception ...................................................................................... 158
Register Bank Error Exception Handling ............................................................. 158
Handling Interrupt Request Signals as Sources for
CPU Interrupt but not DMAC Activation............................................................. 159
Handling Interrupt Request Signals as Sources for
DMAC Activation but not CPU Interrupt............................................................. 159
Break Address Register (BAR)............................................................................. 164
Break Address Mask Register (BAMR) ............................................................... 165
Break Data Register (BDR) .................................................................................. 166