R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 285

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R5S72011

Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
CKIO
SDRAM command
Data bus
CKIO
SDRAM command
Data bus
CKIO
SDRAM command
Data bus
Figure 9.15 Multiple Write Timing Example (Multiple Write of 4 Data Units,
Figure 9.14 Multiple Read Timing Example (Multiple Read of 4 Data Units,
Figure 9.16 Multiple Read Timing Example (Multiple Read of 4 Data Units,
Shortest Timing Settings) Non-Consecutive Read Commands Issued
Shortest Timing Settings) Consecutive Write Commands Issued
Shortest Timing Settings) Consecutive Read Commands Issued
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all command
ACT: Row and bank activation command
RD: Read command
PRA: Precharge-all command
ACT: Row and bank activation command
RD:
PRA: Precharge-all command
DSL: Deselect command
ACT
ACT
ACT
Read command
WR
RD
RD
d0
Multiple read
DSL
WR
RD
d1
Multiple write
WR
RD
RD
d2
d0
d0
Multiple read
DSL
WR
RD
d3
d1
PRA
PRA
RD
d2
d1
Rev. 2.00 Sep. 07, 2007 Page 257 of 1164
Section 9 Bus State Controller (BSC)
DSL
d3
RD
d2
PRA
REJ09B0321-0200
d3

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