R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 717
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
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Table 16.3 SCSMR Settings
The bit rate error in asynchronous is given by the following formula:
Table 16.4 lists examples of SCBRR settings in asynchronous mode, and table 16.5 lists examples
of SCBRR settings in clocked synchronous mode.
Table 16.4 Bit Rates and SCBRR Settings (Asynchronous Mode) (1)
n
0
1
2
3
Bit Rate
(bit/s)
110
150
300
600
1200
2400
4800
9600
19200
31250
38400
Error (%) =
n
2
2
1
1
0
0
0
0
0
0
0
N
88
64
129
64
129
64
32
15
7
4
3
(N + 1) × B × 64 × 2
5
Clock Source
Pφ
Pφ/4
Pφ/16
Pφ/64
Error
(%)
−0.25 2
0.16
0.16
0.16
0.16
0.16
−1.36 0
1.73
1.73
0.00
1.73
Pφ × 10
n
2
1
1
0
0
0
0
0
0
6
2n-1
N
106
77
155
77
155
77
38
19
9
5
4
Section 16 Serial Communication Interface with FIFO (SCIF)
6
− 1
Error
(%)
−0.44 2
0.16
0.16
0.16
0.16
0.16
0.16
−2.34 0
−2.34 0
0.00
−2.34 0
CKS1
0
0
1
1
× 100
Pφ (MHz)
n
2
1
1
0
0
0
0
Rev. 2.00 Sep. 07, 2007 Page 689 of 1164
N
108
79
159
79
159
79
39
19
9
5
4
6.144
SCSMR Settings
Error
(%)
0.08
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
2.40
0.00
CKS0
0
1
0
1
n
2
2
1
1
0
0
0
0
0
0
0
REJ09B0321-0200
N
130
95
191
95
191
95
47
23
11
6
5
7.3728
Error
(%)
–0.07
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
5.33
0.00
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