R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 292

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
Rev. 2.00 Sep. 07, 2007 Page 264 of 1164
REJ09B0321-0200
Note : * Driving the DQM pin high before the initialization sequence is recommended
Reset
Specify all SDRAM control pins as port outputs with the PFC
setting of PORTC to output high level
Channel m settings
(1) Confirm that all status bits in SDSTR have been cleared to 0
(2) Make settings to SDmMOD mode register
(3) Set DRAS, DRCD, DPCG, DCL, and DWR bits in SDmTR
(4) Set DSZ bits in SDmADR
Enable access
SDRAMCm control register operation enable setting
Dummy-read SDRAM area of all channels to be used
Disable access
SDRAMCm control register operation disable setting
Specify SDRAM control pins (except DQM pin*) as SDRAM
with the PFC setting of PORTC
Initialization sequence
(1) Set DPC, DARFC, and DARFI bits in SDIR0
(2) Set DINIRQ bit in SDIR1 to 1
(3) Wait for DINIST bit in SDIR1 to be cleared to 0
Channel m settings
(1) Confirm that all status bits in SDSTR have been cleared to 0
(2) Make settings to SDmMOD mode register
(3) Set DRAS, DRCD, DPCG, DCL, and DWR bits in SDmTR
(4) Set DSZ bits in SDmADR
Start auto-refresh
Set DRFEN bit in SDRFCNT1 to 1
Specify DQM pin as DQM* with the PFC setting of PORTC
Enable access
SDRAMCm control register operation enable setting
SDRAM access enabled
for some SDRAM modules. In this case, the setting may be necessary.
Figure 9.26 SDRAMC Setting Procedure
Perform settings
for all channels
to be used
Perform settings
for all channels
to be used