R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 136
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
- Current page: 136 of 1196
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Section 5 Exception Handling
5.7.2
When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU
operates as follows:
1. The exception service routine start address which corresponds to the vector number specified
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
4. After jumping to the address fetched from the exception handling vector table, program
5.7.3
An instruction placed immediately after a delayed branch instruction is said to be placed in a delay
slot. When the instruction placed in the delay slot is undefined code, an instruction that rewrites
the PC, a 32-bit instruction, an RESBANK instruction, a DIVS instruction, or a DIVU instruction,
slot illegal exception handling starts when such kind of instruction is decoded. The CPU operates
as follows:
1. The exception service routine start address is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the
4. After jumping to the address fetched from the exception handling vector table, program
5.7.4
When undefined code placed anywhere other than immediately after a delayed branch instruction
(delay slot) is decoded, general illegal instruction exception handling starts. The CPU handles
general illegal instructions in the same way as slot illegal instructions. Unlike processing of slot
illegal instructions, however, the program counter value stored is the start address of the undefined
code.
Rev. 2.00 Sep. 07, 2007 Page 108 of 1164
REJ09B0321-0200
in the TRAPA instruction is fetched from the exception handling vector table.
instruction to be executed after the TRAPA instruction.
execution starts. The jump that occurs is not a delayed branch.
delayed branch instruction immediately before the undefined code, the instruction that rewrites
the PC, the 32-bit instruction, the RESBANK instruction, the DIVS instruction, or the DIVU
instruction.
execution starts. The jump that occurs is not a delayed branch.
Trap Instructions
Slot Illegal Instructions
General Illegal Instructions
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