R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 742

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 16 Serial Communication Interface with FIFO (SCIF)
(1)
The data length is fixed at eight bits. No parity bit can be added.
(2)
An internal clock generated by the on-chip baud rate generator by the setting of the C/A bit in
SCSMR and CKE[1:0] in SCSCR, or an external clock input from the SCK pin can be selected as
the SCIF transmit/receive clock.
When the SCIF operates on an internal clock, it outputs the clock signal at the SCK pin. Eight
clock pulses are output per transmitted or received character. When the SCIF is not transmitting or
receiving, the clock signal remains in the high state. When only receiving, the clock signal outputs
while the RE bit of SCSCR is 1 and the number of data in receive FIFO is more than the receive
FIFO data trigger number.
(3)
• SCIF Initialization (Clocked Synchronous Mode)
Before transmitting, receiving, or changing the mode or communication format, the software must
clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF.
Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does
not initialize the RDF, PER, FER, and ORER flags and receive data register (SCRDR), which
retain their previous contents.
Rev. 2.00 Sep. 07, 2007 Page 714 of 1164
REJ09B0321-0200
Transmit/Receive Formats
Clock
Transmitting and Receiving Data