R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 83

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In
Instruction
STC
STC
STC
STC
STC.L
STC.L
STC.L
STS
STS
STS
STS.L
STS.L
STS.L
TRAPA
*
SR,Rn
TBR,Rn
GBR,Rn
VBR,Rn
SR,@-Rn
GBR,@-Rn
VBR,@-Rn
MACH,Rn
MACL,Rn
PR,Rn
MACH,@-Rn
MACL,@-Rn
PR,@-Rn
#imm
practice, the number of instruction execution states in cases such as the following:
a. When there is a conflict between an instruction fetch and a data access
b. When the destination register of a load instruction (memory → register) is the same
In the event of bank overflow, the number of cycles is 19.
as the register used by the next instruction.
Instruction Code
0000nnnn00000010
0000nnnn01001010
0000nnnn00010010
0000nnnn00100010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
0100nnnn00000010
0100nnnn00010010
0100nnnn00100010
11000011iiiiiiii
Operation
SR → Rn
TBR → Rn
GBR → Rn
VBR → Rn
Rn-4 → Rn, SR → (Rn)
Rn-4 → Rn, GBR → (Rn)
Rn-4 → Rn, VBR → (Rn)
MACH → Rn
MACL → Rn
PR → Rn
Rn-4 → Rn, MACH → (Rn)
Rn-4 → Rn, MACL → (Rn)
Rn-4 → Rn, PR → (Rn)
PC/SR → stack area,
(imm × 4 + VBR) → PC
Rev. 2.00 Sep. 07, 2007 Page 55 of 1164
Execu-
tion
Cycles
2
1
1
1
2
1
1
1
1
1
1
1
1
5
T Bit














SH2,
SH2E SH4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
REJ09B0321-0200
Section 2 CPU
Compatibility
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SH-2A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes