R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 138

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Exception Handling
The FPU exception flag field (Flag) of FPSCR is always updated regardless of whether or not an
FPU exception has been accepted, and remains set until explicitly cleared by the user through an
instruction. The FPU exception source field (Cause) of FPSCR changes each time an FPU
instruction is executed.
When the V bit in the FPU exception enable field (Enable) of FPSCR is set and the QIS bit in
FPSCR is also set, FPU exception is generated when qNAN or ±∞ is input to a floating point
operation instruction source.
5.8
When an address error, bus error, FPU exception, register bank error (overflow), or interrupt is
generated immediately after a delayed branch instruction, it is sometimes not accepted
immediately but stored instead, as shown in table 5.11. When this happens, it will be accepted
when an instruction that can accept the exception is decoded.
Table 5.11 Exception Source Generation Immediately after Delayed Branch Instruction
Note:
Rev. 2.00 Sep. 07, 2007 Page 110 of 1164
REJ09B0321-0200
Point of Occurrence
Immediately after a
delayed branch
instruction *
*
When Exception Sources Are Not Accepted
Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF.
Address
Error
Not accepted
Bus Error
Not accepted Not accepted Not accepted Not accepted
Exception Source
FPU
Exception
Register
Bank Error
(Overflow)
Interrupt