R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 55

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(5)
Basic operations are executed between registers. For operations that involve memory access, data
is loaded to the registers and executed (load-store architecture). Instructions such as AND that
manipulate bits, however, are executed directly in memory.
(6)
With the exception of some instructions, unconditional branch instructions, etc., are executed as
delayed branch instructions. With a delayed branch instruction, the branch is taken after execution
of the instruction immediately following the delayed branch instruction. This reduces disturbance
of the pipeline control when a branch is taken.
In a delayed branch, the actual branch operation occurs after execution of the slot instruction.
However, instruction execution such as register updating excluding the actual branch operation, is
performed in the order of delayed branch instruction → delay slot instruction. For example, even
though the contents of the register holding the branch destination address are changed in the delay
slot, the branch destination address remains as the register contents prior to the change.
Table 2.3
(7)
The SH-2A additionally features unconditional branch instructions in which a delay slot
instruction is not executed. This eliminates unnecessary NOP instructions, and so reduces the code
size.
(8)
16-bit × 16-bit → 32-bit multiply operations are executed in one to two cycles. 16-bit × 16-bit +
64-bit → 64-bit multiply-and-accumulate operations are executed in two to three cycles. 32-bit ×
32-bit → 64-bit multiply and 32-bit × 32-bit + 64-bit → 64-bit multiply-and-accumulate
operations are executed in two to four cycles.
SH-2A CPU
BRA
ADD
Load-Store Architecture
Delayed Branch Instructions
Unconditional Branch Instructions with No Delay Slot
Multiply/Multiply-and-Accumulate Operations
TRGET
R1,R0
Delayed Branch Instructions
Executes the ADD before
branching to TRGET.
Description
Rev. 2.00 Sep. 07, 2007 Page 27 of 1164
Example of Other CPU
ADD.W
BRA
R1,R0
TRGET
REJ09B0321-0200
Section 2 CPU