R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 48

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
2.1.2
The control registers consist of four 32-bit registers: the status register (SR), the global base
register (GBR), the vector base register (VBR), and the jump table base register (TBR).
The status register indicates instruction processing states.
The global base register functions as a base address for the GBR indirect addressing mode to
transfer data to the registers of on-chip peripheral modules.
The vector base register functions as the base address of the exception handling vector area
(including interrupts).
The jump table base register functions as the base address of the function table area.
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Rev. 2.00 Sep. 07, 2007 Page 20 of 1164
REJ09B0321-0200
Initial value:
Initial value:
Status Register (SR)
R/W:
R/W:
Bit:
Bit:
Control Registers
—
31
15
—
R
R
0
0
R/W
BO
—
31
31
31
31
30
14
R
0
0
R/W
CS
—
29
13
R
0
0
14
BO
—
28
12
—
R
R
0
0
13
CS
Figure 2.2 Control Registers
27
—
11
—
R
R
0
0
9
M
GBR
VBR
TBR
Q
8
7
26
—
10
—
R
R
0
0
6
I[3:0]
5
R/W
25
—
—
R
M
0
9
4
3
R/W
2
24
—
—
R
Q
0
8
1
S
0
0
0
0
T
R/W
23
—
R
0
7
1
Status register (SR)
Global base register (GBR)
Vector base register (VBR)
Jump table base register (TBR)
R/W
22
—
R
0
6
1
I[3:0]
R/W
21
—
R
0
5
1
R/W
20
—
R
0
4
1
19
—
—
R
R
0
3
0
18
—
—
R
R
0
2
0
R/W
17
—
—
R
0
1
S
R/W
16
—
—
R
0
0
T