R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 49

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
31 to 15
14
13
12 to 10
9
8
7 to 4
3, 2
1
0
Bit Name
—
BO
CS
—
M
Q
I[3:0]
—
S
T
Initial
Value
All 0
0
0
All 0
—
—
1111
All 0
—
—
R/W
R
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
BO Bit
Indicates that a register bank has overflowed.
CS Bit
Indicates that, in CLIP instruction execution, the value
has exceeded the saturation upper-limit value or fallen
below the saturation lower-limit value.
Reserved
These bits are always read as 0. The write value
should always be 0.
M Bit
Q Bit
Used by the DIV0S, DIV0U, and DIV1 instructions.
Interrupt Mask Level
Reserved
These bits are always read as 0. The write value
should always be 0.
S Bit
Specifies a saturation operation for a MAC instruction.
T Bit
True/false condition or carry/borrow bit
Rev. 2.00 Sep. 07, 2007 Page 21 of 1164
REJ09B0321-0200
Section 2 CPU