R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 371
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
- Current page: 371 of 1196
- Download datasheet (8Mb)
Figure 11.2 Examples of the Alternation of Bus Mastership between the DMAC
Cycle steal transfer mode (transfer between different BIU)
Cycle steal transfer mode (transfer in the same BIU)
Pipeline transfer mode (transfer between different BIU)
System clock
System clock
System clock
DMAC
CPU
DMAC
CPU
DMAC
CPU
(1) CPU access to other than BIU on DMAC read side is possible
(2) CPU access to other than BIU on DMAC write side is possible
(3) CPU access to other than BIU on DMAC read/write side is possible
(4) CPU access to other than BIU on DMAC read side is possible
(5) CPU access to other than BIU on DMAC read/write side is possible
(6) CPU access to other than BIU on DMAC write side is possible
and CPU in Various DMA Transfer Modes
Read
Read
Read
(1)
(3)
(4)
Single operand transfer
Single operand transfer
Single operand transfer
Read
Write
Write
Read
Write
(2)
(3)
(5)
Read
Read
Read
Write
(1)
Write
(6)
Section 11 Direct Memory Access Controller (DMAC)
Write
Write
Write
(2)
(3)
Rev. 2.00 Sep. 07, 2007 Page 343 of 1164
Read
Read
Read
(1)
(3)
(4)
Single operand transfer
Single operand transfer
Single operand transfer
Read
Read
Write
Write
Write
(2)
(3)
(5)
Read
Read
Read
Write
(1)
Write
(6)
REJ09B0321-0200
Write
Write
Write
(2)
(3)
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