GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 38

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 3-1: Clock_Phase_Offset[15:0] Encoding Scheme
VID_STD[5:0]
Setting
1
3-6, 39-42
7-20, 25-38, 43-46
21-23, 47-51
Note: Program Clock_Phase_Offset = 0000 0000 0000 0000b to achieve a zero clock phase offset.
Output Video Clock
Frequency
f
20MHz < f
40MHz < f
f
PCLK
PCLK
< 20MHz
> 80MHz
PCLK
PCLK
< 40MHz
< 80MHz
•
The encoding scheme for the Clock_Phase_Offset register (1Dh) is shown in
Table
step size will depend on the frequency of the output video clock.
NOTE: If VID_STD[5:0] = 63 and the reference format is changed, care must be
taken to ensure that the Clock_Phase_Offset register is correctly programmed for
the new output format before the reference is applied.
The value programmed in the H_Offset register (1Bh) must not exceed the
maximum number of clock periods per line of the outgoing video standard.
Similarly, the value programmed in the V_Offset register (1Ch) must not exceed
the maximum number of lines per frame of the outgoing standard. Both horizontal
and vertical offsets will be in the positive direction. Negative offsets (advances) are
achieved by programming a value in the appropriate register equal to the maximum
allowable offset minus the desired advance.
NOTES:
1. The device will delay all output timing signals by 2 PCLKs relative to the input
36655 - 2
V_Offset (1Ch) - the difference between the reference VSYNC signal and the
output V Sync and/or V Blanking in lines, with a control range of zero to +1
frame. All line-based timing output signals will be delayed by the vertical offset
programmed in this register.
HSYNC reference. This will occur even when the H_Offset register is not
programmed. The user may compensate for this delay by subtracting 2 PCLK
cycles from the desired horizontal offset before loading the value into the host
interface.
3-1. The offset programmed will be in the positive direction. Note that the
Step Size
(Fraction
of a
PCLK)
-------- -
512
-------- -
256
-------- -
128
April 2006
----- -
64
1
1
1
1
Maximum
Number of
Steps
511
255
127
63
Bits Required to
Set the Number
of Steps
b
b
8
b
7
b
b
b
7
6
b
b
6
5
b
b
6
5
b
5
b
4
GS4911B/GS4910B Data Sheet
b
b
5
4
b
b
4
3
b
b
4
3
b
b
3
2
3
b
2
b
b
b
2
1
b
b
2
1
b
b
1
0
b
1
0
b
0
0
Clock_Phase_Offset
[15:0] Settings
b
b
b
8
b
7
000001b
6
000010b
5
000100b
001000b
8
7
b
6
b
5
b
7
b
6
b
5
b
4
b
6
000b
5
b
4
b
00b
5
4
b
0b
4
3
b
38 of 113
3
3
b
3
b
b
2
b
2
2
b
2
b
b
1
b
1
1
b
1
b
b
0
b
0
0
0