GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 63

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

3.7.2 Audio Clock Synthesis (GS4911B only)
The programmable audio clock generator is referenced to the internal PCLK signal
and is responsible for generating the ACLK output signals. Three audio clock
output pins, ACLK1 to ACLK3, are available to the application layer.
The fundamental sampling frequency, fs, is selected using the ASR_SEL[2:0] pins
as shown in
the host interface (see
If desired, the external ASR_SEL[2:0] pins may be ignored by setting bit 2 of the
Audio_Control register and the sampling frequency may instead be programmed
in the ASR_SEL[2:0] register of the host interface (see
Although the external ASR_SEL[2:0] pins will be ignored, they should not be left
floating.
Table 3-7: Audio Sample Rate Select
When all three ASR_SEL[2:0] pins are set LOW, the audio clock outputs will be
high impedance. In this case, the application layer may continue to power the
AUD_PLL_VDD pin; however, to minimize noise and power consumption,
AUD_PLL_VDD may be grounded.
By default, after system reset, ACLK1 to ACLK3 will output clock signals at 256fs,
64fs, and fs respectively. Different division ratios for each output pin may be
selected by programming the ACLK_fs_Multiple registers beginning at address
3Fh of the host interface (see
register is shown in
64fs, fs, and z bit are selectable on a pin by pin basis. The z bit will go HIGH for
one fs period every 192 fs periods. Its phase is not defined by any timing event in
the GS4911B, and so is arbitrary.
36655 - 2
*Slow 32, 44.1, and 48 are available only when the video standard selected is 23.98, 29.97, or 59.94
frame rate based. They refer to 32kHz, 44.1kHz, or 48kHz multiplied by 1000/1001 to maintain the 1,
2, or 3 frame sequence normally associated with 24, 30, and 60 fps video.
ASR_SEL[2:0]
April 2006
Table
000
001
010
011
100
101
110
111
3-7. Once selected, the audio clock rate may be customized via
Table
Section 3.9 on page
3-8. Clock outputs of 512fs, 348fs, 256fs, 192fs, 128fs,
Section 3.12.3 on page
GS4911B/GS4910B Data Sheet
72).
Sampling Frequency (kHz)
Audio Clock Generation Disabled
Section 3.12.3 on page
Slow 44.1*
79). The encoding of this
Slow 32*
Slow 48*
44.1
32
48
96
63 of 113
79).