GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 44

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GS4910B

Manufacturer Part Number
GS4910B
Description
HD/SD/Graphics Clock and Timing Generator with GENLOCK
Manufacturer
GENNUM [Gennum Corporation]
Datasheet
3.4.2 10FID
Timing for Graphics Formats
The GS4911B/GS4910B is pre-programmed to recognize the timing for 16
different graphics formats presented to the input reference pins. These graphic
formats are described in
The supported graphics standards are all progressive, and do not use the FSYNC
signal. Therefore, FSYNC should be held LOW by the application layer. The VESA
formats supported have a 0.5% frequency tolerance.
VSYNC transitions are typically co-timed with the leading edge of HSYNC. The
duration and polarity of these signals for each format is listed in
NOTE: The user must ensure that the input HSYNC polarity for VID_STD [5:0] = 47
and 49 – 54 be active LOW.
The 10FID input is a reset pin, which can be used to reset the divider for the 10FID
output signal. In the GS4911B, the 10FID input pin will also reset the divider for the
AFS output signal. This default setting may be modified using the Audio_Control
register of the host interface (see
The GS4911B will reset the phase of the audio clocks to the leading edge of the H
Sync output on line 1 of every output frame in which the 10FID input is HIGH. This
enables the user to reset the phase of the dividers when generating custom signals
via the host interface (see
If the input reference format does not include a 10 Field ID signal, the external
10FID input pin should be held LOW.
The timing of the 10FID input signal is shown in
Horizontal Sync Input
Figure 3-5: 10FID Input Timing
36655 - 2
10FID Input
April 2006
Section 1.4 on page
Section 3.7.2.1 on page
Line 1 every n frames where:
n = 5 @ 29.97 fps, 30 fps
n = 10 @ 59.94 fps, 60 fps
Line 1, Frame 1 every 'n' frames
Section 3.12.3 on page
Total Line
GS4911B/GS4910B Data Sheet
20.
Figure
65).
3-5.
79).
Table
1-2.
44 of 113

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