GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 95

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 3-13: Configuration and Status Registers (Continued)
Register Name
RSVD
Video_Control
VID_STD[5:0]
Clocks_Per_Line
Clocks_Per_Hsync
Hsync_To_SAV
Hsync_To_EAV
Address
4Bh
4Ch
4Ch
4Ch
4Ch
4Ch
4Dh
4Dh
4Eh
4Fh
50h
51h
36655 - 2
15-0
15-0
Bit
–
15-5
4
3-2
1
0
15-6
5-0
15-0
15-0
April 2006
Contains the number of output video clock cycles from
Contains the number of output video clock cycles from
Description
Reserved.
Reserved. Set these bits to zero when writing to 4Ch.
10FID_F_pulse - set this bit HIGH to stretch the 10FID
pulse duration from 1 line to 1 field.
Reference:
Reserved. Set these bits to zero when writing to 4Ch.
Host_VID_STD - set this bit HIGH to select the output
video standard using register 4Dh instead of the
external VID_STD[5:0] pins.
The external VID_STD[5:0] pins will be ignored, but
should not be left floating.
Reference:
Reserved. Set this bit to zero when writing to 4Ch.
Reserved. Set these bits to zero when writing to 4Dh.
Replaces the external VID_STD[5:0] pins when
VID_From_Host (bit 1 of address 4Ch) is HIGH.
Reference:
Contains the number of output video clock cycles per
line for the selected output timing format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference:
Contains the number of output video clock cycles in the
active H Sync interval for the selected output timing
format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference:
the start of H Sync to the start of active video for the
selected output timing format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference:
the start of H Sync to the end of active video for the
selected output timing format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference:
Section 3.8.1 on page 67
Section 1.4 on page 20
Section 1.4 on page 20
Section 3.10 on page 74
Section 3.10 on page 74
Section 3.10 on page 74
Section 3.10 on page 74
GS4911B/GS4910B Data Sheet
R/W
–
–
R/W
–
R/W
–
–
R/W
R/W
R/W
R/W
R/W
Default
–
–
0
–
0
–
–
00h
–
–
–
–
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