GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 87

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Constcf_Genlock
RSVD
Video_Cap_Genlock
Video_Res_Genlock
Address
24h
24h
24h
25h
26h
26h
27h
27h
36655 - 2
15-8
15-6
15-6
Bit
7-3
2-0
–
5-0
5-0
April 2006
Crash_Time - controls the crash lock period of video
Reserved. Set these bits to zero when writing to 26h.
Reserved. Set these bits to zero when writing to 27h.
Description
PLL locking process. This time contributes to the total
PLL Lock Time given in the AC Characteristics Table.
The time of the crash process in H reference periods is
determined by [Crash_Time x 4] + 1.
The default value of these bits will vary depending on
the output video standard selected.
Reference:
Lock_Lost_Threshold - controls the threshold of the lock
indication circuit. A larger value programmed in this
register can increase the stability of the LOCK_LOST
output signal when the input H reference signal is
subject to large amounts of low frequency jitter. A larger
value in this register will also increase the lock indication
time, although not the actual lock time of the device.
The default value of these bits will vary depending on
the output video standard selected.
Run_Window - controls the output frequency error in the
case of a missing or mis-timed H reference transition.
The default value of this register allows the device to
maintain genlock through one missing input H pulse.
This feature can be disabled by programming
Run_Window = 000b. In this case, the device will
immediately react to any disturbance of the input H
signal.
The default value of these bits will vary depending on
the output video standard selected.
Reference:
Reserved.
Control signal to adjust loop bandwidth of video genlock
block.
The value programmed in this register must be between
10 and Video_Res_Genlock - 21.
The default value of this register will vary depending on
the output video standard selected.
Reference:
Control signal to adjust loop bandwidth of video genlock
block.
The value programmed in this register must be between
32 and 42.
The default value of this register will vary depending on
the output video standard selected.
Reference:
Section 3.6.3 on page 58
Section 3.5.3 on page 47
Section 3.6.4 on page 58
Section 3.6.4 on page 58
GS4911B/GS4910B Data Sheet
R/W
R/W
R/W
R/W
–
–
R/W
–
R/W
Default
–
–
–
–
–
–
–
–
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