GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 62

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 3-6: Video Clock Phase Adjustment Host Settings
PCLKn_Phase[3:0] Setting
Phase Increment (ns)
NOTES:
1. The phase increments listed above are nominal values.
2. The phase of PCLK is delayed relative to the TIMING_OUT pins.
0h
0
0.7
Although the external VID_STD[5:0] pins will be ignored, they should not be left
floating.
NOTE: If VID_STD[5:0] is set to 62 on power-up, the video clock will run at a
frequency based on the internal default settings of the chip until the user programs
registers 20h to 23h. Please see
of custom clock generation.
Once the video clock has been generated, it will be presented to the application
layer via the PCLK1 to PCLK3 pins. By default, each of the 3 video clock outputs
will produce the generated fundamental clock frequency. However, it is possible to
select other rates for each PCLK output by programming the PCLK_Phase/Divide
registers beginning at address 2Ch of the host interface (see
page
Each PCLK output may be individually programmed to provide one of the following:
•
•
•
When all six VID_STD[5:0] pins are set LOW, the video clocks will be disabled.
PCLK1 and PCLK2 will go LOW and PCLK3/PCLK3 will be high impedance.
NOTE: If the PCLK divider bits of registers 2Ch - 2Eh are set to enable a divide by
2 or divide by 4, the resultant divided clock will align with the falling edge of the
output H Sync timing signal either on its rising or falling edge.
The PCLK1 to PCLK3 outputs may also be individually delayed with respect to the
eight TIMING_OUT signals to allow for skew control downstream from the
GS4911B/GS4910B. Using the PCLK_Phase/Divide registers, the phase of each
clock may be delayed up to a nominal 10.3ns in 16 steps of approximately 700ps
each
phase adjustment described in
Additionally, the current drive capability of PCLK1 and PCLK2 may be set high or
low using the PCLK_Phase/Divide registers. By default the current drive will be
low. It must be set high if the clock rate is greater than 100MHz.
36655 - 2
1h
PCLK fundamental frequency
Fundamental frequency /2
Fundamental frequency /4
(Table
79).
1.4
2h
2.1
3h
April 2006
3-6). This delay is available in addition to the genlock timing offset
2.8
4h
3.5
5h
4.2
6h
Section 3.2.1 on page
Section 3.9 on page 72
4.9
7h
5.6
8h
GS4911B/GS4910B Data Sheet
6.3
9h
7.0
Ah
37.
7.7
Bh
for a detailed explanation
Ch
8.4
Section 3.12.3 on
9.1
Dh
9.8
Eh
62 of 113
10.3
Fh