GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 80

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Input_Standard
Amb_Std_Sel
Reference_Standard_Disable
Address
0Fh
0Fh
0Fh
0Fh
10h
10h
14h-11h
36655 - 2
15-11
63-0
Bit
15-13
12
11-6
5-0
10-0
April 2006
Reserved. Set these bits to zero when writing to 10h.
The Reference_Standard_Disable registers may be
Description
Reserved. Set these bits to zero when writing to 0Fh.
Force_Input - Set this bit HIGH to force the
GS4911B/GS4910B to recognize the applied input
reference format as the standard programmed in bits
11-6 of this register.
Reference:
Forced_Standard - When bit 12 is set HIGH, the
GS4911B/GS4910B will use the value programmed in
these bits, rather than the value in bits 5-0, to determine
the input reference format. The 6-bit value programmed
here should always correspond to the VID_STD[5:0]
value of the applied reference.
These bits should only be programmed as part of the
Freeze mode procedure described in
page
Detected_Standard - Contains the video standard
applied to the input reference pins once it has been
detected. These bits are set by the Reference Format
Detector block and correspond to the VID_STD[5:0]
value of the standard as listed in
The Detected_Standard bits will be set to zero if no input
reference signal is applied or if the input reference
signal is not an automatically recognized video format.
Otherwise the value will be between 1 and 54.
Reference:
The user may set this register to distinguish between
different formats that look identical to the internal
Reference Format Detector block. See
Reference:
used to disable one or more of the recognized input
standards from being used to genlock the output. This is
done by setting the bit HIGH that corresponds to the
VID_STD[5:0] value of the video standard in
For example, if bit 5 is set HIGH, then the output clock
and timing signals will not genlock to an input reference
with timing corresponding to VID_STD[5:0] = 5 in
Table
Address 11h = bits 15-0
Address 12h = bits 31-16
Address 13h = bits 47-32
Address 14h = bits 63-48
Reference:
40.
1-2.
Section 3.2.1.2 on page 40
Section 3.5.2 on page 45
Section 3.5.2.1 on page 46
Section 3.6 on page 50
GS4911B/GS4910B Data Sheet
Table
Section 3.2.1.2 on
Table
1-2.
Table
3-2.
1-2.
R/W
–
R/W
R/W
R/W
–
R/W
R/W
Default
–
0
0
N/A
–
0
0
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