GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 75

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

3.11 Extended Audio Mode for HD Demux using the Gennum Audio
Core
The GS4911B/GS4910B has been designed to interface with Gennum's FPGA
Audio Core in order to provide a 24.576MHz clock (512 * 48kHz) locked to the
audio clock contained in the embedded audio data packets of an HD-SDI stream.
It is the responsibility of the user to divide this clock by 4 to obtain the 6.144MHz
required by the core.
In HD Demux mode, the FPGA Audio Core will extract an audio clock from the
embedded audio data packets and present a 24kHz clock to the
GS4911B/GS4910B via the aclkdiv2a (for Group A) and aclkdiv2b (for Group B)
outputs. The embedded clock must be 48kHz.
The 24kHz reference signals for each audio group must be applied to the HSYNC
input pin of a GS4911B/GS4910B, while a divided version of this signal must be
applied to the VSYNC input pin. The divided signal must meet the requirements for
VSYNC validity given in
VSYNC signal be generated by dividing the 24kHz reference applied to HSYNC by
512 to give 46.875Hz.
To enable the extended audio mode, the user must do the following:
1. Set VID_STD[5:0] = 04h.
2. Set the F_Lock_Mask and V_Lock_Mask bits [4:3] of register address 16h to
3. Set the Ext_Audio_Mode register address 81h to 20C1h.
4. Toggle the Update_Custom_V_Clock bit [6] of register address 16h.
In this mode, the GS4911B/GS4910B will produce a 24.576MHz clock on its PCLK
output pins that is locked to the 24kHz extracted audio clock reference applied to
HSYNC. It will not lock to any other reference frequency. The user may then divide
this frequency by 4 using the programmable dividers in the GS4911B/GS4910B.
Serial
Video
Figure 3-13: Audio Clock Block Diagram for HD Demux Operation
36655 - 2
Input
1.
/512
/512
Deserializer
GS49xxB
GS49xxB
April 2006
GS1559
Video Data
PCLK
PCLK1
PCLK1
Section 3.5.2 on page
aclkdiv2b
aclkdiv2a
aclk128a
aclk128b
vin[19:0]
pclk
GS4911B/GS4910B Data Sheet
FPGA
DEMUX CORE
45. It is recommended that the
HD AUDIO
aclk64a
wclka
aout1_2
aout3_4
aclk64b
wclkb
aout5_6
aout7_8
75 of 113