FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 115

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

UART Power Management
Direct power management is controlled by
CR22. Refer to CR22 for more information.
Auto Power Management is enabled by CR23-
B4 and B5.
following auto power management operations:
1.
2.
Note:
Exit Auto Powerdown
The transmitter exits powerdown on a write to
the XMIT buffer.
powerdown when RXDx changes state.
Parallel Port
Direct power management is controlled by
CR22. Refer to CR22 for more information.
Auto Power Management is enabled by CR23-
B3. When set, this bit allows the ECP or EPP
logical parallel port blocks to be placed into
powerdown when not being used.
The EPP logic is in powerdown under any of the
following conditions:
1.
2.
The transmitter enters auto powerdown
when the transmit buffer and shift register
are empty.
The receiver enters powerdown when the
following conditions are all met:
A. Receive FIFO is empty
B. The receiver is waiting for a start bit.
EPP is not enabled in the configuration
registers.
EPP is not selected through ecr while in
ECP mode.
While in powerdown the Ring Indicator
interrupt is still valid and transitions
when the RI input changes.
When set, these bits allow the
The receiver exits auto
115
The ECP logic is in powerdown under any of the
following conditions:
1.
2
Exit Auto Powerdown
The parallel port logic can change powerdown
modes when the ECP mode is changed through
the ecr register or when the parallel port mode is
changed through the configuration registers.
V
This chip requires a (TBD) MicroAmp battery
supply (V
registers. These registers retain the contents of
the general purpose registers and wake-up
event registers. The RTC and CMOS registers
are also battery backed up.
configuration of the Consumer IR wake-up
functionality is not battery backed-up.
V
The FDC37B78x requires a 25 mA trickle supply
(V
programmable wake-up events in the Soft
Power Management logic, SCI, PME and SMI
interfaces when V
FDC37B78x is not intended to provide wake-up
capabilities on standby current, V
connected to V
receiver, IR interface, the CIR run-time registers,
the PME configuration registers, and the PME
interface. The V
on-Reset signal to initialize certain components.
All wakeup event registers and related logic are
battery backed-up to retain the configuration of
the wakeup events upon a power loss (i.e., V
= 0 V and V
on a V
BAT
TR
TR
Support
)
ECP is not enabled in the configuration
registers.
SPP, PS/2 Parallel port or EPP mode is
selected through ecr while in ECP mode.
Support
BAT
to
POR.
BAT
provide
TR
) to provide battery backed up
= 0 V). These registers are reset
CC
. V
TR
pin generates a V
CC
TR
sleep
powers the Consumer IR
is removed.
current
Note: The
TR
TR
for
can be
Power-
If the
the
CC