FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 138

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

RTC INTERFACE
The ISA interface is functionally compatible with
the 8042-style host interface. It consists of the
D0-7 data bus, the nIOR, nIOW and the Status
*Bank 0 is at 70h. Bank 1 is relocatable via the RTC Mode Register and the Secondary Base Address
for RTC Bank 1 (CR62 and CR63). See Configuration section.
RTC Address Register
Writing to this register sets the CMOS address
that will be read or written.
RTC Data Register
A read of this register will read the contents of
the selected CMOS register.
register will write to the selected CMOS register.
REAL TIME CLOCK
The Real Time Clock is a complete time of day
clock with a day of month alarm, calendar (up to
the year 9999), a programmable periodic
interrupt, and a programmable square wave
generator.
Features
Counts seconds, minutes, and hours of the day.
Counts days of the week, date, month, year and
century.
Day of Month Wake-Up Alarm
Binary or BCD representation of time, calendar
and alarms.
Three interrupts - each is separately software
maskable. (No daylight savings time)
256 Bytes of CMOS RAM.
ISA ADDRESS*
Addresses 0x60, 0x64, 0x70 and 0x71 are qualified by AEN
0x70
0x71
Base* + 1
Base*
(R/W)
(R/W)
A write to this
Table 61 - ISA I/O Address Map
RTC Bank 1 Address Register
RTC Bank 1 Data Register
BLOCK
RTC
RTC
138
register, Input Data register, and Output Data
register. Table 61 shows how the interface
decodes the control signals. In addition to the
above signals, the host interface includes
keyboard and mouse IRQs.
Port Definition and Description
OSCILLATOR
Crystal Oscillator input. A 32.768 kHz crystal
connected externally on the XTAL1 and XTAL2
pins generates the 32.768 kHz RTC input clock.
Maximum clock frequency is 32.768 KHz.
RTC Reset
The clock, calendar, or RAM functions are not
affected by the system reset (RESET_DRV
active).
(i.e., system reset) and the battery voltage is
above 1 volt nominal, the following occurs:
1)
2)
3)
4)
5)
6)
7)
8)
9)
Address Register
Data Register
Periodic Interrupt Enable (PIE) is cleared to
0.
Alarm Interrupt Enable (AIE) bit is cleared
to 0.
Update Ended Interrupt Enable (UIE) bit is
cleared to 0.
Update Ended Interrupt Flag (UF) bit is
cleared to 0.
Interrupt Request Status Flag (IRQF) bit is
cleared to 0.
Periodic Interrupt Flag (PIF) is cleared to 0.
The RTC and CMOS registers are not
accessible.
Alarm Interrupt Flag (AF) is cleared to 0.
nIRQ pin is in high impedance state.
When the RESET_DRV pin is active
FUNCTION