FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 116

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

PLL CONTROL
BIT (CR24.1)
Internal PWRGOOD
An internal PWRGOOD logical control is
included to minimize the effects of pin-state
uncertainty in the host interface as V
and off. When the internal PWRGOOD signal is
“1” (active), V
host interface is active.
PWRGOOD signal is “0” (inactive), V
and the FDC37B78x host interface is inactive;
that is, ISA bus reads and writes will not be
decoded.
The FDC37B78x device pins nPME, KCLK,
MCLK, IRRX, nRI1, nRI2, RXD1, RXD2, nRING,
Button_In and GP53 are part of the PME
interface and remain active when the internal
PWRGOOD signal has gone inactive, provided
V
CLK32OUT pins remain active when the internal
PWRGOOD is inactive and V
When the internal PWRGOOD is inactive, and
VTR is powered, the GPIOs (excluding GP53)
become tri-state (input) and are able to generate
wake-up events.
signal is also used to determine the clock
source for the CIrCC CIR and to disable the IR
Half Duplex Timeout.
32.768 kHz Standby Clock Output
The FDC37B78x provides a 32.768 kHz trickle clock output pin. This output is active as long as V
present.
TR
is powered. In addition, the nPowerOn and
1
0
0
0
0
cc
is > 4V, and the FDC37B78x
POWER BIT
CIR PLL
The internal PWRGOOD
TABLE 51 - FDC37B78x PLL CONTROLS AND SELECTS
X
0
0
1
1
When the internal
TR
PWRGOOD
INTERNAL
is powered.
cc
cc
cycles on
is
X
0
1
0
1
4V,
116
All PLLs Powered Down
32KHz PLL Unpowered, Not Selected,
14MHz PLL Powered, Selected.
32KHz PLL Powered, Selected,
14MHz PLL Unpowered, Not Selected.
32KHz PLL Powered, Not Selected, 14MHz PLL
Powered, Selected.
Note: If V
wake-up events when V
be at its full minimum potential at least 10 s
before V
and V
difference between the two supplies must not
exceed 500mV.
CIRCC PLL Power Control
The FDC37B78x uses the 32.768 kHz RTC
clock and a clock multiplier (PLL) to drive the
CIrCC Wakeup function when V
removed. The CIR PLL Power bit, located in the
Sleep/Wake Configuration Register, is used to
enable (power-up) the 32.768 kHz clock PLL.
When the CIR PLL Power bit is set to “1”
(active), the 32.768 kHz clock PLL is running
and can replace the 14.318 MHz clock source
for the CIR Wake Event, depending upon the
state of the internal PWRGOOD signal (TABLE
51). When the CIR PLL Power bit is reset to “0”
(inactive/default), the 32.768 kHz clock PLL is
unpowered.
cc
cc
TR
begins a power-on cycle. When V
are fully powered, the potential
is to be used for programmable
DESCRIPTION
CC
is removed, V
cc
has been
TR
must
TR
TR
is