FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 133

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

Status Register
This register is cleared on a reset. This register
is read-only for the Host and read/write by the
FDC37B78x CPU.
UDWritable by FDC37B78x CPU.
are user-definable.
C/D(Command Data)-This bit specifies whether
the input data register contains data or a
command (0 = data, 1 = command). During a
host data/command write operation, this bit is
set to "1" if SA2 = 1 or reset to "0" if SA2 = 0.
IBF(Input Buffer Full)- This flag is set to 1
whenever the host system writes data into the
input data register. Setting this flag activates
the FDC37B78x CPU's nIBF (MIRQ) interrupt if
enabled. When the FDC37B78x CPU reads the
input
automatically reset and the interrupt is cleared.
There is no output pin associated with this
internal signal.
data
register
KCLK
KDAT
MCLK
MDAT
Host I/F Data Reg
Host I/F Status Reg
(DBB),
DESCRIPTION
this
These bits
TABLE 60 - RESETS
N/A: Not Applicable
bit
is
133
HARDWARE RESET (RESET)
OBF(Output Buffer Full) - This flag is set to
whenever the FDC37B78x CPU write to the
output data register (DBB). When the host
system reads the output data register, this bit is
automatically reset.
EXTERNAL CLOCK SIGNAL
The FDC37B78x Keyboard Controller clock
source is a 12 MHz clock generated from a
14.318 MHz clock. The reset pulse must last for
at least 24 16 MHz clock periods. The pulse-
width requirement applies to both internally (Vcc
POR) and externally generated reset signals. In
powerdown mode, the external clock signal is
not loaded by the chip.
DEFAULT RESET CONDITIONS
The FDC37B78x has one source of reset: an
external reset via the RESET_DRV pin. Refer to
TABLE 60 for the effect of each type of reset on
the internal registers.
Input
Input
Input
Input
00H
N/A