FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 136

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

Bit 1 of Port 92, the ALT_A20 signal, is used to
force nA20M to the CPU low for support of real
mode compatible software.
externally OR’ed with the A20GATE signal from
the keyboard controller and CPURST to control
the nA20M input of the CPU. Writing a 0 to bit 1
of the Port 92 Register forces ALT_A20 low.
ALT_A20 low drives nA20M to the CPU low, if
A20GATE from the keyboard controller is also
low. Writing a 1 to bit 1 of the Port 92 Register
forces ALT_A20 high. ALT_A20 high drives
nA20M to the CPU high, regardless of the state
of A20GATE from the keyboard controller.
Upon reset, this signal is driven low.
Note: When Port 92 is disabled,
writes are ignored and reads
return undefined values.
P92
8042
Bit 0
P20
Pulse
Gen
This signal is
14us
KRST_GA20
Bit 2
KRESET Generation
6us
14us
136
KRST
8042 P17 Functions
8042 function P17 is implemented as in a true
8042 part.
timing. A port signal of 0 drives the output to 0.
A port signal of 1 causes the port enable signal
to drive the output to 1 within 20-30nsec. After
several (# TBD) clocks, the port enable goes
away and the internal 90µA pull-up maintains
the output signal as 1.
In 8042 mode, the pins can be programmed as
open drain. When programmed in open drain
mode, the port enables do not come into play. If
the port signal is 0 the output will be 0. If the
port signal is 1, the output tristates: an external
pull-up can pull the pin high, and the pin can be
shared i.e., P17 and nSMI can be externally tied
together. In 8042 mode, the pins cannot be
nALT_RST
6us
Reference the 8042 spec for all
KBDRST