FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 166

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

EITHER EDGE TRIGGERED INTERRUPTS
Four GPIO pins are implemented that allow an
interrupt to be generated on both a high-to-low
and a low-to-high edge transition, instead of one
or the other as selected by the polarity bit.
The either edge triggered interrupts function as
follows: Selecting the Either Edge Triggered
Interrupt (EETI) function for these GPIO pins is
applicable when the combined interrupt is
enabled for the GPIO pin (GPINT1 for GP10-
GP17, and GPINT2 for GP50-GP54 and GP60-
GP67). Otherwise, selection of the EETI
function will produce no function for the pin. If
Miscellaneous Status Register
The MSC_STS register is implemented as follows to hold the status bits of these four GPIOs.
Miscellaneous Status Register (PM1_STS)
Register Location: <PM1_BLK>+16h System I/O Space
Default Value: 00h on Vbat POR
Attribute: Read/Write (Note 0)
Size: 8-bits
0
1
2
3
4
5-7
BIT
EETI1_STS
EETI2_STS
EETI3_STS
EETI4_STS
VTRPOR_STS
Reserved
NAME
Either Edge Triggered Interrupt Input 1 Status. This bit is set when
an edge occurs on the GP11 pin. This bit is cleared by writing a 1
to this bit position (writing a 0 has no effect).
Either Edge Triggered Interrupt Input 2 Status. This bit is set when
an edge occurs on the GP12 pin. This bit is cleared by writing a 1
to this bit position (writing a 0 has no effect).
Either Edge Triggered Interrupt Input 3 Status. This bit is set when
an edge occurs on the GP53 pin. This bit is cleared by writing a 1
to this bit position (writing a 0 has no effect).
Either Edge Triggered Interrupt Input 4 Status. This bit is set when
an edge occurs on the GP54 pin. This bit is cleared by writing a 1
to this bit position (writing a 0 has no effect).
This bit is set upon VTR POR. This bit is cleared by writing a 1 to
this bit position (writing a 0 has no effect). Additionally, when the
system turns on (nPowerOn active low) due to a VTR POR, then
an SCI is generated.
Reserved. This bit always returns zero.
166
the EETI function is selected for the GPIO pin,
then the bits that control input/output, polarity
and open collector/push-pull have no effect on
the function of the pin. However, the polarity bit
does affect the value of the GP bit (i.e., register
GP1, bit 2 for GP12).
An interrupt occurs if the status bit is set and the
interrupt is enabled.
which of the EETI interrupts transitioned. These
status bits are located in the MSC_STS register.
The status is valid whether or not the interrupt is
enabled and whether or not the EETI function is
selected for the pin.
DEFINITION
The status bits indicate