FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 143

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

REGISTER B (BH)
SET
When the SET bit is a "0", the update functions
normally by advancing the counts once per
second. When the SET bit is a "1", an update
cycle in progress is aborted and the program
MSB
SET
b7
RS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
OSCILLATOR
FREQUENCY
32.768 KHz
32.768 KHz
32.768 KHz
32.768 KHz
32.768 KHz
RATE SELECT
PIE
RS2
b6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
AIE
b5
DV2
Table 67 - Periodic Interrupt Rates
REGISTER A BITS
Table 66 - Divider Selection Bits
0
0
0
0
1
1
RS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DV1
UIE
0
0
1
1
0
1
b4
PERIOD RATE OF
1.953125 ms
INTERRUPT
143
3.90625 ms
3.90625 ms
122.070 s
244.141 s
488.281 s
976.562 s
DV0
7.8125 ms
7.8125 ms
15.625 ms
31.25 ms
62.5 ms
X
X
0
1
0
1
125 ms
250 ms
500 ms
may initialize the
without an update occurring in the middle of
initialization. SET is a read/write bit which is
not modified by RESET_DRV or any internal
functions.
0.0
RES
b3
32.768 KHz TIME BASE
Reset Divider
Reset Divider
Normal Operate
Test
Test
Reset Divider
DM2
b2
MODE
FREQUENCY OF
time
INTERRUPT
8.192 KHz
4.096 KHz
2.048 KHz
1.024 KHz
256 Hz
128 Hz
512 Hz
256 Hz
128 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
24/12
and
b1
calendar bytes
DSE
LSB
b0