XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 103

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

7.5.3 Port C Pulldown Devices
7.5.4 Port C Logic
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
DDRC7–DDRC0 — Port C Data Direction Bits
All port C pins can have software programmable pulldown devices
enabled or disabled globally by the SWPDI bit in the MOR. These
pulldown devices are individually controlled by the write-only pulldown
register A (PDRA) shown in
pins (PC7–PC4) and PDICL controls the lower four pins (PC3–PC0).
Clearing the PDICH or PDICL bits in the PDRA turns on the pulldown
devices if the port C pin is an input. Reading the PDRA returns undefined
results since it is a write-only register. Reset clears the PDICH and
PDICL bits, which turns on all the port C pulldown devices.
Figure 7-15
When a port C pin is programmed as an output, reading the port bit
actually reads the value of the data latch and not the voltage on the pin
itself. When a port C pin is programmed as an input, reading the port bit
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its DDR bit.
operations of the port C pins.
Address:
Reset:
These read/write bits control port C data direction. Reset clears the
DDRC7–DDRC0 bits.
Read:
Write:
1 = Corresponding port C pin configured as output and pulldown
0 = Corresponding port C pin configured as input
$0006
DDRC7
device disabled
Bit 7
Figure 7-14. Data Direction Register C (DDRC)
0
shows the I/O logic of port C.
Parallel Input/Output
DDRC6
6
0
DDRC5
5
0
Figure
DDRC4
4
0
7-3. PDICH controls the upper four
Table 7-4
DDRC3
3
0
Port C (28-Pin Versions Only)
summarizes the
DDRC2
2
0
Advance Information
Parallel Input/Output
DDRC1
1
0
DDRC0
Bit 0
0
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