XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 86

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Parallel Input/Output
7.3.2 Data Direction Register A
Advance Information
86
The contents of the port A data direction register (DDRA) determine
whether each port A pin is an input or an output. Writing a logic 1 to a
DDRA bit enables the output buffer for the associated port A pin. A
DDRA bit set to a logic 1 also disables the pulldown device for that pin.
Writing a logic 0 to a DDRA bit disables the output buffer for the
associated port A pin. The upper two bits always read as logic 0s. A reset
initializes all DDRA bits to logic 0s, configuring all port A pins as inputs
and disabling the voltage comparators from driving PA4 or PA5.
DDRA5–DDRA0 — Port A Data Direction Bits
Address:
Reset:
These read/write bits control port A data direction. Reset clears the
DDRA5–DDRA0 bits.
Read:
Write:
1 = Corresponding port A pin configured as output and pulldown
0 = Corresponding port A pin configured as input
$0004
device disabled
Bit 7
Figure 7-2. Data Direction Register A (DDRA)
0
0
Parallel Input/Output
= Unimplemented
6
0
0
DDRA5
5
0
DDRA4
MC68HC705JJ7 • MC68HC705JP7 — REV 4
4
0
DDRA3
3
0
DDRA2
2
0
DDRA1
1
0
MOTOROLA
DDRA0
Bit 0
0