XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 57

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

4.6.2 PA0–PA3 Pins
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
NOTE:
NOTE:
The response of the IRQ/V
capability of the PA0 through PA3 pins is enabled. If the port A pins are
enabled as external interrupts, then any high level on a PA0–PA3 pin will
cause the IRQ changes and state to be ignored until all of the PA0–PA3
pins have returned to a low level.
Programming the PIRQ bit in the MOR to a logic 1 enables the PA0–PA3
pins (PA0:3) to serve as additional external interrupt sources. A rising
edge on a PA0:3 pin latches an external interrupt request. After
completing the current instruction, the CPU tests the IRQ latch. If the
IRQ latch is set, the CPU then tests the I bit in the condition code register
and the IRQE bit in the ISCR. If the I bit is clear and the IRQE bit is set,
the CPU then begins the interrupt sequence. The CPU clears the IRQ
latch while it fetches the interrupt vector, so that another external
interrupt request can be latched during the interrupt service routine. As
soon as the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request.
The PA0:3 pins can be edge-triggered or edge- and level-triggered.
External interrupt triggering sensitivity is selected by the LEVEL bit in the
MOR.
With the edge- and level-sensitive trigger MOR option, a rising edge or
a high level on a PA0:3 pin latches an external interrupt request. The
edge- and level-sensitive trigger MOR option allows connection to a
PA0:3 pin of multiple wired-OR interrupt sources. As long as any source
is holding the pin high, an external interrupt request is present, and the
CPU continues to execute the interrupt service routine.
With the edge-sensitive only trigger MOR option, a rising edge on a
PA0:3 pin latches an external interrupt request. A subsequent external
interrupt request can be latched only after the voltage level of the
previous interrupt signal returns to a logic 0 and then rises again to a
logic 1.
If the port A pins are enabled as external interrupts, then a high level on
any PA0:3 pin will drive the state of the IRQ function such that the
Interrupts
PP
pin can be affected if the external interrupt
Advance Information
External Interrupts
Interrupts
57