XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 154

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Core Timer
Advance Information
154
NOTE:
CTOFE — Core Timer Overflow Interrupt Enable Bit
RTIE — Real-Time Interrupt Enable Bit
CTOFR — Core Timer Overflow Flag Reset Bit
RTIFR — Real-Time Interrupt Flag Reset Bit
RT1 and RT0 — Real-Time Interrupt Select Bits 1 and 0
Changing RT1 and RT0 when a COP timeout is imminent or uncertain
may cause a real-time interrupt request to be missed or an additional
real-time interrupt request to be generated. Clear the COP timer just
before changing RT1 and RT0.
This read/write bit enables core timer overflow interrupts. Reset
clears CTOFE.
This read/write bit enables real-time interrupts. Reset clears RTIE.
Writing a logic 1 to this write-only bit clears the CTOF bit. CTOFR
always reads as a logic 0. Reset does not affect CTOFR.
Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR
always reads as a logic 0. Reset does not affect RTIFR.
These read/write bits select one of four real-time interrupt rates, as
shown in
COP watchdog, changing the real -time interrupt rate also changes
the counting rate of the COP watchdog. Reset sets RT1 and RT0,
selecting the longest COP timeout period and longest real-time
interrupt period.
1 = Core timer overflow interrupts enabled
0 = Core timer overflow interrupts disabled
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
1 = Clear CTOF flag bit
0 = No effect on CTOF flag bit
1 = Clear RTIF flag bit
0 = No effect on RTIF flag bit
Table
10-1. Because the selected RTI output drives the
Core Timer
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA