XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 169

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
9B
...
...
B7
B6
BF
...
...
9A
Writing to the OCRH before writing to the OCRL inhibits timer compares
until the OCRL is written. Reading or writing to the OCRL after reading
the TCR will clear the output compare flag bit (OCF). The output
compare OLVL state will be clocked to its output latch regardless of the
state of the OCF.
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use this procedure:
A software example of this procedure is shown in
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to the OCRH. Compares are now inhibited until OCRL is
3. Read the TSR to arm the OCF for clearing.
4. Enable the output compare registers by writing to the OCRL. This
5. Enable interrupts by clearing the I bit in the condition code register.
written.
also clears the OCF flag bit in the TSR.
16
13
17
Table 11-1. Output Compare Initialization Example
Programmable Timer
SEI
...
...
STA
LDA
STX
...
...
CLI
OCRH
TSR
OCRL
DISABLE INTERRUPTS
.....
.....
INHIBIT OUTPUT COMPARE
ARM OCF FLAG FOR CLEARING
READY FOR NEXT COMPARE, OCF CLEARED
.....
.....
ENABLE INTERRUPTS
Output Compare Registers
Table
Programmable Timer
Advance Information
11-1.
169