XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 62

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Interrupts
4.9 Serial Interrupts
4.10 Analog Interrupts
Advance Information
62
The TOF flag bit is cleared by a read of the TSR with the TOF flag bit set,
and then followed by an access to the LSB of the timer registers (TMRL)
or by reset. The TOIE enable bit is unaffected by reset.
The simple serial interface can generate the following interrupts:
Setting the I bit in the condition code register disables serial interrupts.
The controls for these interrupts are in the serial control register (SCR)
located at $000A and in the status bits in the serial status register (SSR)
located at $000B.
A transfer complete interrupt occurs if the serial interrupt flag (SPIF)
becomes set while the serial interrupt enable bit (SPIE) is also set. The
SPIF flag bit is in the serial status register (SSR) located at $000B, and
the SPIE enable bit is located in the serial control register (SCR) located
at $000A. The SPIF flag bit is cleared by a read of the SSR with the SPIF
flag bit set, and then followed by a read or write to the serial data register
(SDR) located at $000C. The SPIF flag bit can also be reset by writing a
one to the SPIR bit in the SCR.
The analog subsystem can generate the following interrupts:
•
•
•
•
•
Receive sequence complete
Transmit sequence complete
Voltage on positive input of comparator 1 is greater than the
voltage on the negative input of comparator 1.
Voltage on positive input of comparator 2 is greater than the
voltage on the negative input of comparator 2.
Trigger of the input capture interrupt from the programmable timer
as described in
Interrupts
4.8.1 Input Capture Interrupt
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA