XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 93

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

7.4.5 PB0, PBI, PB2, and PB3 Logic
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
WRITE $0001
WRITE $0005
READ $0001
WRITE $0011
RESET
READ $0005
The typical I/O logic shown in
PB3 pins of port B. When these port B pins are programmed as an
output, reading the port bit actually reads the value of the data latch and
not the voltage on the pin itself. When these port B pins are programmed
as an input, reading the port bit reads the voltage level on the pin. The
data latch can always be written, regardless of the state of its DDRB bit.
The operations of the PB0–PB3 pins are summarized in
The PB0–PB3 pins share their inputs with another module. When using
the other attached module, these conditions must be observed:
1. If the DDRB configures the pin as an output, then the port data
2. If the DDRB configures the pin as an input, then reading the port
3. If DDRB configures the pin as an input and the pulldown device is
R
R
Figure 7-8. PB0–PB3 Pin I/O Circuit
register can provide an output which may conflict with any external
input source to the other module. The pulldown device will be
disabled in this case.
data register will return the state of the input in terms of the digital
threshold for that pin (analog inputs will default to logic states).
activated for a pin, it will also load the input to the other module.
PORT BDATA
REGISTER
DATA DIRECTION
BIT PBx
REGISTER B
PULLDOWN
REGISTER B
BIT DDRBx
BIT PDIBx
Parallel Input/Output
Figure 7-8
MASK OPTION REG. ($1FF1)
is used for PB0, PB1, PB2, and
(PINS PB0, PB1, PB2, PB3)
TIMER INPUT CAPTURE
ANALOG SUBSYSTEM,
AND PROGRAMMABLE
Advance Information
Parallel Input/Output
PULLDOWN
DEVICE
Table
PBx
7-2.
Port B
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