XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 42

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Memory
2.5 User and Interrupt Vector Mapping
2.6 Random-Access Memory (RAM)
Advance Information
42
NOTE:
The interrupt vectors are contained in the upper memory addresses
above $1FF0 as shown in
The 224 addresses from $0020 to $00FF serve as both the user RAM
and the stack RAM. The central processor unit (CPU) uses five RAM
bytes to save all CPU register contents before processing an interrupt.
During a subroutine call, the CPU uses two bytes to store the return
address. The stack pointer decrements during pushes and increments
during pulls.
Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
Address
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FF0
$1FF1
$1FF2
$1FF3
$1FF4
$1FF5
$1FF6
$1FF7
$1FF8
$1FF9
$1FFF
Memory
Figure 2-4. Vector Mapping
Figure
COP Register and EPROM Security
Core Timer Interrupt Vector (MSB)
Core Timer Interrupt Vector (LSB)
Analog Interrupt Vector (MSB)
Analog Interrupt Vector (LSB)
Serial Interrupt Vector ((LSB)
Serial Interrupt Vector (MSB)
Timer Interrupt Vector (MSB)
Timer Interrupt Vector (LSB)
External IRQ Vector (MSB)
External IRQ Vector (LSB)
Mask Option Register
MC68HC705JJ7 • MC68HC705JP7 — REV 4
Reset Vector (MSB)
Reset Vector (LSB)
2-4.
Register Name
SWI Vector (MSB)
SWI Vector (LSB)
MOTOROLA