S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 108

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

Bus Operating Modes
Note: ADV must remain LOW for page mode operation.
108
Asynchronous Mode
ADDRESS
LB#/UB#
CellularRAM products incorporate a burst mode interface found on Flash products
targeting low-power, wireless applications. This bus interface supports asynchro-
nous, page mode, and burst mode read and write transfers. The specific interface
supported is defined by the value loaded into the BCR. Page mode is controlled
by the refresh configuration register (RCR[7]).
CellularRAM products power up in the asynchronous operating mode. This mode
uses the industry standard SRAM control bus (CE#, OE#, WE#, LB#/ UB#).
READ operations
LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the
specified access time has elapsed. WRITE operations
CE#, WE#, and LB#/ UB# are driven LOW. During asynchronous WRITE opera-
tions, the OE# level is a “Don't Care,” and WE# will override OE#. The data to be
written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs
first). Asynchronous operations (page mode disabled) can either use the ADV
input to latch the address, or ADV can be driven LOW during the entire READ/
WRITE operation.
During asynchronous operation, the CLK input must be held static (HIGH or LOW,
no transitions). WAIT will be driven while the device is enabled and its state
should be ignored.
DATA
WE#
OE#
CE#
Don't Care
V CC Q
V CC
V CC = 1.7 V
Figure 23. READ Operation (ADV# LOW)
(Figure
Figure 22. Power-Up Initialization Timing
23) are initiated by bringing CE#, OE#, and LB#/UB#
A d v a n c e
Device Initialization
t PU > 150 µs
CellularRAM Type 2
t RC = READ Cycle Time
Address Valid
I n f o r m a t i o n
Device ready for
normal operation
(Figure
Data Valid
24) occur when
cellRAM_00_A0 October 4, 2004