S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 155
S71GS128NB0
Manufacturer Part Number
S71GS128NB0
Description
128N based MCPs
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71GS128NB0.pdf
(195 pages)
- Current page: 155 of 195
- Download datasheet (3Mb)
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay; burst
October 4, 2004 cellRAM_00_A0
DQ[15:0]
LB#/UB#
A[22:0]
length four; burst wrap enabled.
ADV#
WAIT
WE#
OE#
CE#
CLK
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V OH
V OL
READ Burst Identified
High-Z
(WE# = LOW)
t CSP
t SP
t SP
A d v a n c e
Address
t SP t HD
Valid
t CEW
t HD
t HD
Figure 52. Burst WRITE Operation
(Note 2)
I n f o r m a t i o n
CellularRAM Type 2
t CLK
t KHTL
t SP
t SP
D[1]
t HD
t KP
t HD
D[2]
t KP
t KHKL
D[3]
Legend:
D[0]
t HD
t HZ
t OHZ
t CBPH
Don't Care
High-Z
155
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