S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 145

no-image

S71GS128NB0

Manufacturer Part Number
S71GS128NB0
Description
128N based MCPs
Manufacturer
SPANSION [SPANSION]
Datasheet
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. OE# can stay LOW during burst suspend. If OE# is LOW, DQ[15:0] will continue to output valid data.
October 4, 2004 cellRAM_00_A0
DQ[15:0]
LB#/UB#
A[22:0]
ADV#
WAIT
WE#
CE#
OE#
CLK
Symbol
t
t
t
t
t
t
t
t
CBPH
ACLK
t
t
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V OH
V OL
BOE
KOH
OHZ
CSP
OLZ
CLK
HD
HZ
High-Z
t SP
Address
t CSP
t SP
t HD
t SP
t SP
Valid
t CEW
High-Z
t HD
t HD
t HD
Table 42. Burst READ Timing Parameters—Burst Suspend
12.5
Min
A d v a n c e
5
4
2
2
5
t OLZ
t ACLK
70ns/80 MHz
t BOE
t CLK
OUTPUT
VALID
t KOH
Figure 46. READ Burst Suspend
OUTPUT
VALID
I n f o r m a t i o n
Max
20
9
8
8
CellularRAM Type 2
OUTPUT
VALID
OUTPUT
VALID
t OHZ
Min
15
5
5
2
2
5
(Note 2)
85ns/66 MHz
t OLZ
t BOE
Max
OUTPUT
11
20
VALID
8
8
Legend:
OUTPUT
VALID
Don't Care
t HZ
t OHZ
High-Z
t CBPH
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address
Valid
Undefined
145

Related parts for S71GS128NB0