S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 11

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

Input/Output Descriptions
December 17, 2004 S71GS256/128N_00_A0
A23-A0
A22-A0
DQ15-DQ0
OE#
WE#
V
NC
F-RST#
WP#/ACC
R-CE1#
ZZ#
CRE
F1-CE#
F-V
R-V
R-UB#
R-LB#
RFU
RY/BY#
F-V
R-V
SS
CC
IO
CC
IO
A d v a n c e
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I n f o r m a t i o n
24 Address inputs (256 Mb)
23 Address inputs (128 Mb)
Data input/output
Output Enable input. Asynchronous relative to CLK
for the Burst mode.
Write Enable input.
Ground
No Connect; not connected internally
Hardware reset input. Low = device resets and
returns to reading array data
Hardware write protect input / programming
acceleration input.
Chip-enable input for pSRAM.
pSRAM Sleep mode
Configuration Register Enable. CRE is used only for
power savings, but does not enable burst
operations.
Chip-enable input for Flash 1.
Flash 3.0 Volt-only single power supply.
pSRAM Power Supply.
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM).
Reserved for future use.
Ready/Busy output.
Flash Input/Output Buffer Power Supply
pSRAM Input/Output Buffer Power Supply
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