S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 130

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. Low-Z to High-Z timings are tested with the circuit shown in
3. High-Z to Low-Z timings are tested with the circuit shown in
130
CE# HIGH between Subsequent Mixed-Mode Operations
transition from either V
transition away from the High-Z (V
Burst to READ Access Time (Variable Latency)
Chip Disable to DQ and WAIT High-Z Output
Output Disable to DQ High-Z Output
CE# Setup Time to Active CLK Edge
Hold Time from Active CLK Edge
Burst OE# LOW to Output Delay
Output Enable to Low-Z Output
Setup Time to Active CLK Edge
Address Setup to ADV# HIGH
CLK to DQ High-Z Output
CE# LOW to WAIT Valid
CLK HIGH or LOW Time
Output HOLD from CLK
CLK Rise or Fall Time
CLK to Low-Z Output
CLK to Output Delay
CLK to WAIT Valid
CLK Period
Parameter
OH
or V
Table 32. Burst READ Cycle Timing Requirements
OL
toward V
CC
Q/2) level toward either V
CC
A d v a n c e
Q/2.
CellularRAM Type 2
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CBPH
ACLK
KHKL
KHTL
t
t
CEW
KOH
t
OHZ
t
ABA
AVS
BOE
CLK
CSP
KHZ
OLZ
KLZ
HD
HZ
KP
SP
I n f o r m a t i o n
Figure
Figure
OH
12.5
Min
70ns/80 MHz
10
5
4
2
3
2
2
3
5
3
1
or V
38. The High-Z timings measure a 100mV
38. The Low-Z timings measure a 100mV
OL
.
Max
7.5
1.6
35
20
9
8
9
8
5
8
Min
10
15
85ns/66 MHz
5
1
5
2
3
2
2
3
5
3
Max
7.5
1.6
55
11
20
11
cellRAM_00_A0 October 4, 2004
8
8
5
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
2
2
3