S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 132

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

132
Initialization Period (required before normal operations)
Timing Diagrams
Chip Disable to WAIT High-Z Output
Setup Time to Activate CLK Edge
Hold Time from Active CLK Edge
CE# Setup to CLK Active Edge
CLK HIGH or LOW Time
CLK Rise or Fall Time
Clock to WAIT Valid
Clock Period
Table 34. Burst WRITE Cycle Timing Requirements (Continued)
Parameter
Parameter
V CC , V CC Q = 1.7V
Table 35. Initialization Timing Parameters
Figure 39. Initialization Period
A d v a n c e
CellularRAM Type 2
Symbol
t
t
t
t
Symbol
KHKL
KHTL
t
t
t
t
CLK
CSP
HD
HZ
KP
SP
t PU
t
PU
I n f o r m a t i o n
12.5
Min
70ns/80 MHz
Min
4
2
3
3
70ns/80 MHz
Max
1.6
Max
150
normal operation
8
9
Device ready for
V CC (MIN)
Min
15
85ns/66 MHz
Min
85ns/66 MHz
5
2
3
3
Max
1.6
Max
150
11
cellRAM_00_A0 October 4, 2004
8
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
µs
Notes
Notes