S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 123
S71GS128NB0
Manufacturer Part Number
S71GS128NB0
Description
128N based MCPs
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71GS128NB0.pdf
(195 pages)
- Current page: 123 of 195
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October 4, 2004 cellRAM_00_A0
All must be set to "0"
RCR[2]
RCR[19]
0
0
0
0
1
1
1
1
0
1
Reserved
22–20
RCR[7]
0
1
A[22:20]
Register Select
Select RCR
Select BCR
RCR[6]
RCR[1]
Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This
feature allows the device to reduce standby current by refreshing only that part
of the memory array required by the host system. The refresh options are full ar-
ray, one-half array, one-quarter array, three-quarters array, or none of the array.
The mapping of these partitions can start at either the beginning or the end of
the address map (see
1
0
0
1
0
0
1
1
0
0
1
1
Register
Select
Page Mode Enable/Disable
19
Page Mode Disabled (default)
Page Mode Enable
RCR[5]
A19
All must be set to "0"
1
0
1
0
RCR[0]
A d v a n c e
Reserved
Table 23. 128Mb Address Patterns for PAR (RCR[4] = 1)
0
1
0
1
0
1
0
1
Table 22. Refresh Configuration Register Mapping
18–8
Maximum Case Temp
+85ºC (default)
+70ºC
+45ºC
+15ºC
A[18:8]
Page
One-quarter of die
One-quarter of die
Table 23
ACTIVE SECTION
One-eighth of die
One-eighth of die
One-half of die
One-half of die
7
None of die
A7
Full die
I n f o r m a t i o n
TCR
CellularRAM Type 2
6
through
A6
5
A5
RCR[4]
DPD
0
1
Table
4
A4
Must be set to "0"
000000h–7FFFFFh
000000h–3FFFFFh
000000h–1FFFFFh
000000h–0FFFFFh
400000h–7FFFFFh
600000h–7FFFFFh
700000h–7FFFFFh
25).
ADDRESS SPACE
Reserved
Deep Power-Down
DPD Enable
DPD Disable (default)
3
RCR[2]
A3
0
0
0
0
1
1
1
1
0
RCR[1] RCR[0]
1
1
1
1
0
0
0
0
2
A2
PAR
1
A1
0
1
0
1
0
1
1
0
8 Meg x 16
4 Meg x 16
2 Meg x 16
1 Meg x 16
0 Meg x 16
4 Meg x 16
2 Meg x 16
1 Meg x 16
SIZE
0
A0
Refresh Coverage
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
Top 1/2 array
Top 1/4 array
Top 3/4 array
Address Bus
Read Configuration
Register
DENSITY
128Mb
64Mb
32Mb
16Mb
64Mb
32Mb
16Mb
0Mb
123
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