S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 161

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes
October 4, 2004 cellRAM_00_A0
DQ[15:0]
LB#/UB#
HIGH, it must remain HIGH for at least 5ns (t
Extended Timings Impact CellularRAM™ Operation”
A[22:0]
ADV#
WAIT
WE#
OE#
CE#
CLK
Symbol
t
t
t
t
t
t
t
t
WHZ
CKA
AW
BW
CW
DW
WC
DH
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V OH
V OL
V IH
V IL
High-Z
t WHZ
Address
Figure 56. Asynchronous WRITE (ADV# LOW) Followed By Burst READ
Valid
t WC
t CW
t WP t WPH
Table 54. Asynchronous WRITE Timing Parameters—ADV# LOW
DATA
t DH
t WC
Min
A d v a n c e
70
70
70
70
23
70
t AW
0
t BW
Address
t DW
Valid
DATA
t WC
70ns/80 MHz
t WR
t CKA
(Note 2)
t CSP
I n f o r m a t i o n
Max
CBPH
8
CellularRAM Type 2
t CSP
t SP
Address
t SP
t SP
V OH
V OL
t SP
Valid
) to schedule the appropriate internal refresh operation. See
t HD
t HD
t HD
t HD
for restrictions on the maximum CE# LOW time (t
High-Z
t CEW
t CLK
Min
85
85
85
85
23
85
0
t BOE
t ACLK
85ns/66 MHz
Output
Valid
t KOH
Output
Valid
Legend:
Max
8
Output
Valid
Don't Care
Output
Valid
Units
t OHZ
CEM
ns
ns
ns
ns
ns
ns
ns
ns
Undefined
High-Z
).
“How
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