S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 178

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

Low Power Operation
178
ADDRESS
LB# / UB# Operation
Standby Mode Operation
Temperature Compensated Refresh
LB#/UB#
DATA
WE#
OE#
CE#
Page mode takes advantage of the fact that adjacent addresses can be read in a
shorter period of time than random addresses. WRITE operations do not include
comparable page mode functionality.
The lower byte (LB#) enable and upper byte (UB#) enable signals allow for byte-
wide data transfers. During READ operations, enabled bytes are driven onto the
DQs. The DQs associated with a disabled byte are put into a High-Z state during
a READ operation. During WRITE operations, any disabled bytes will not be trans-
ferred to the memory array and the internal value will remain unchanged. During
a WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#,
LB#, or UB#, whichever occurs first.
When both the LB# and UB# are disabled (HIGH) during an operation, the device
will disable the data bus from receiving or transmitting data. Although the device
will seem to be deselected, the device remains in an active mode as long as CE#
remains LOW.
During standby, the device current consumption is reduced to the level necessary
to perform the DRAM refresh operation on the full array. Standby operation oc-
curs when CE# and ZZ# are HIGH and there are no transactions in progress.
The device will enter standby operation during READ and WRITE operations
where the address and control inputs remain static for an extended period of
time. This “active” standby mode will continue until a change occurs to the ad-
dress or control inputs.
Temperature compensated refresh (TCR) is used to adjust the refresh rate de-
pending on the device operating temperature. DRAM technology requires more
Figure 68. Page Mode READ Operation
ADD[0]
t AA
A d v a n c e
CellularRAM-2A
D[0]
ADD[1]
t APA
I n f o r m a t i o n
D[1]
ADD[2]
t APA
D[2]
ADD[3]
t APA
D[3]
cellRAM_02_A0 December 15, 2004
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