BT848 ETC, BT848 Datasheet - Page 122

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

C
Interrupt Status
Interrupt Status
Memory Mapped Location 0x100 – (INT_STAT)
This register provides status of pending interrupt conditions. To clear the interrupts, read this register, then write the
same data back. A 1 in the write data clears the particular register bit. The interrupt /status bits can be polled at any
time.
112
Bits
ONTROL
[31:28]
[23:20]
[27]
[26]
[25]
[24]
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
R
EGISTER
Type
RO
RO
RO
RO
RO
RO
RR
RR
RR
RR
RR
RR
RR
RR
D
Default
0000
0
0
0
0
0
0
0
0
EFINITIONS
Name
RISCS
RISC_EN
Reserved
RACK
FIELD
Reserved
SCERR
OCERR
PABORT
RIPERR
PPERR
FDSR
FTRGT
FBUS
Description
Set when RISC status set bits are set in the RISC instruction.
Reset when RISC status reset bits are set. Status only, no inter-
rupt.
A value of 0 indicates the DMA controller is currently disabled. Sta-
tus only, no interrupt.
Set when I
receiver does not acknowledge, then this bit will be reset when
I2CDONE is set. Status only, no interrupt.
0 = Odd field, 1 = Even field. Status only, no interrupt.
Set when the DMA EOL sync counter overflows. This is a severe
error which requires the software to restart the field capture pro-
cess. Also set when SYNC codes do not match in the data/instruc-
tion streams.
Set when the DMA controller detects a reserved/unused opcode in
the instruction sequence, or reserved/unused sync status in a
SYNC instruction. In general, this includes any detected RISC
instruction error.
Set whenever the initiator receives a MASTER or TARGET
ABORT.
Set when a data parity error is detected (Parity Error Response
must be set) while the initiator is reading RISC instructions.
RISC_ENABLE is reset by the target to stop the DMA immediately.
Set when a parity error is detected on the PCI bus for any of the
transactions, R/W, address/data phases, initiator/target,
issued/sampled PERR regardless of the Parity Error Response bit.
All parity errors are serious except for data written to display.
FIFO Data Stream Resynchronization occurred. The number of
pixels, lines, or modes passing through FIFO does not match RISC
program expectations.
Set when a pixel data FIFO overrun condition results in the master,
terminating the transaction due to excessive target latency.
Set when a pixel data FIFO overrun condition is being handled by
dropping as many DWORDs as needed, indicating bus access
latencies are long.
L848A_A
2
C operation is completed successfully. Otherwise, if the
Single-Chip Video Capture for PCI
Bt848/848A/849A
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