BT848 ETC, BT848 Datasheet - Page 59

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

Bt848/848A/849A
Single-Chip Video Capture for PCI
Brooktree
RISC Program Setup and
RISC Instructions
Synchronization
®
There are two independent sets of RISC instructions in the host memory, one for
the odd field and the other for the even field. The first field begins with a synchro-
nization instruction (See SYNC in Table 11) indicating packed or planar data from
the FIFO (STATUS[3:0] = FM1 or FM3), and it ends with a SYNC instruction in-
dicating an even or an odd field to follow (STATUS[3:0] = VRE or VRO). The sec-
ond field begins with a SYNC instruction and ends with a SYNC instruction
followed by a JUMP instruction back to the first field. The SYNC instructions al-
low the synchronization of the FIFO output and the RISC program start/end points.
quence in the host memory for the odd and even fields. The DMA controller nor-
mally branches through the RISC instruction sequence via JUMP instructions. The
RISC program sequence only needs to be changed when the parameters of the vid-
eo capture/preview mode change, otherwise the DMA controller continuously cy-
cles through the same program which is set up once for control of an entire frame.
There exist five types of packed mode RISC instructions (WRITE, WRITEC,
SKIP, SYNC, JUMP) to control the data stored in the FIFO. Three additional pla-
nar mode instructions exist, which replace the simple packed mode WRITE/SKIP
instructions. Instruction details are listed in Table 11. The DMA controller switch-
es from packed mode to planar mode or vice versa based on the status codes flow-
ing through the FIFOs along with the pixel data.
The software will set up a pixel data flow by creating a RISC instruction se-
L848A_A
F
UNCTIONAL
DMA Controller
D
ESCRIPTION
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