BT848 ETC, BT848 Datasheet - Page 74

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

E
Input Interface
64
Single Crystal Operation
LECTRICAL
(Bt848A/849A Only)
I
NTERFACES
The Bt848A/849A includes an internal phase locked loop that may be used to de-
code NTSC and PAL using only a single crystal. When using the PLL, a
28.636363 MHz, 50 ppm, fundamental (or third overtone) crystal must be con-
nected to XT0.
operation PLL_I should be set to zero. In this mode, the correct clock frequency is
already input to the system and the PLL is shut down. An out of lock or error con-
dition is indicated by the PLOCK bit in the PSTATUS register.
the following sequence must be followed: Initially, TGCKI bits in the TGCTRL
register must be programmed for normal operation of the XTAL ports. After the
PLL registers are programmed, the PLOCK bit in the DSTATUS register must be
polled until it has been verified that the PLL has attained lock (approximately 500
ms). At that point the TGCKI bits are set to select operation via the PLL.
This clock is used to generate the CLKx2 frequency via the following equation:
These values should be programmed as follows to generate PAL frequencies:
The PLL can be put into low power mode by setting PLL_I to zero. For NTSC
When using the PLL to generate the required NTSC and PAL clock frequencies
Frequency = (F_input / PLL_X) * PLL_I.PLL_F/PLL_C
where
PAL (CLKx2 = 35.46895 MHz)
L848A_A
F_input = 28.63636 MHz (50 ppm)
PLL_X = Reference pre-divider
PLL_I = Integer input
PLL_F = Fractional input
PLL_C = Post divider
PLL_X = 1
PLL_I = 0x0E
PLL_F = 0xDCF9
PLL_C = 0
Single-Chip Video Capture for PCI
Bt848/848A/849A
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